(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of fabricating dual-metal transistors having different work functions in the fabrication of integrated circuits.
(2) Description of the Prior Art
It is anticipated that a single metal gate with mid-gap work function values will not be suitable for CMOS applications due to buried channel effects. By using a single metal gate for both NMOSFET and PMOSFET, the threshold voltage becomes too high for both types of transistors. In order to achieve a lower threshold voltage, additional implantation is required and this will result in buried channel effects. The short channel effect control will then be degraded. However, with dual metal gates having different work functions, additional implantation is not required. That is, one electrode with a lower work function will be used in the NMOSFET while another electrode with a higher work function will be used for the PMOSFET. That means that the threshold voltage for NMOSFET and PMOSFET can be tailored independently. It is desired to maintain the conventional CMOS process flow in the dual metal gate process.
U.S. Pat. No. 6,043,157 to Gardner et al shows a process for forming dual gates where one gate is polysilicon and the other gate is metal. U.S. Pat. No. 6,087,231 to Xiang et al discloses a dummy gate process where amorphous gates doped with different dopants are formed. U.S. Pat. No. 6,083,836 to Rodder teaches a dummy gate process where two gates are formed. For example, one gate is polysilicon and the other is aluminum. U.S. Pat. No. 5,266,519 to Iwamoto teaches oxidation of a metal film to be used as an anti-plating mask.